EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 227

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Figure 7–20. Simplified Diagram of the DQS Phase-Shift Circuitry for Arria II Devices
Notes to
(1) All features of the DQS phase-shift circuitry are accessible from the UniPHY IP core and ALTMEMPHY megafunction in the Quartus II software.
(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For the exact PLL and input
(3) Phase offset settings can only go to the DQS logic blocks.
(4) DQS delay settings can go to the logic array and DQS logic block.
December 2010 Altera Corporation
clock pin, refer to
Input Reference
Figure
Clock (2)
7–20:
clk
Table 7–6
DLL
Figure 7–20
reference clock goes into the DLL to a chain of up to 16 delay elements. The phase
comparator compares the signal coming out of the end of the delay chain block to the
input reference clock. The phase comparator then issues the upndn signal to the
Gray-coded counter. This signal increments or decrements a 6-bit delay setting (DQS
delay settings) that increases or decreases the delay through the delay element chain
to bring the input reference clock and the signals coming out of the delay element
chain in phase.
You can reset the DLL from either the logic array or a user I/O pin. Each time the DLL
is reset, you must wait for 1,280 clock cycles for the DLL to lock before you can
capture the data properly.
Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals
by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°, 120°, 135°, 144°, 180°, or 240°. The
shifted DQS signal is then used as the clock for the DQ IOE input registers.
All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal
phase shifted by a different degree amount but all must be referenced at one
particular frequency. For example, you can have a 90° phase shift on DQS1T and a 60°
phase shift on DQS2T, referenced from a 200-MHz clock. Not all phase-shift
combinations are supported. The phase shifts on the DQS pins referenced by the same
DLL must all be a multiple of 22.5° (up to 90°), 30° (up to 120°), 36° (up to 144°), 45°
(up to 180°), or 60° (up to 240°).
Comparator
aload
Phase
and
Table
Delay Chains
upndninclkena
7–10.
upndnin
shows the DQS phase-shift circuitry for Arria II devices. The input
Up/Down
Counter
6
6
offsetdelayctrlout [5:0]
offsetdelayctrlout [5:0]
delayctrlout [5:0]
dqsupdate
Arria II Device Handbook Volume 1: Device Interfaces and Integration
offsetdelayctrlin [5:0]
offsetdelayctrlin [5:0]
6
DQS Delay
Settings
addnsub
addnsub
Phase offset settings
from the logic array
Phase offset settings
from the logic array
(Note 1)
( offset [5:0] )
(4)
6
6
(dll_offset_ctrl_b)
(dll_offset_ctrl_a)
Control
Control
Phase
Phase
Offset
Offset
B
A
( offset [5:0] )
6
6
(offsetctrlout [5:0])
(offsetctrlout [5:0])
DLL0 phase offset
settings to bottom side,
DLL1 phase offset settings
to right and top side of the
device (3)
settings to top and right
side, DLL1 phase offset
settings to bottom side of
the device (3)
DLL0 phase offset
7–31