EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 440

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–54
Figure 1–53. Transceiver Configurations in Basic Double-Width Mode with a 16-Bit PMA-PCS Interface for Arria II
Devices
Notes to
(1) The maximum data rate specification shown in
(2) The byte ordering block is available only if you select the word alignment pattern length of 16 or 32 bits.
(3) Arria II GX I3 devices can support up to 6.375 Gbps. For more information, refer to the
Arria II Device Handbook Volume 2: Transceivers
Figure
1–53:
Data Rate (Gbps)
Functional Mode
Data Rate (Gbps) (1)
Number of Channels
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz) (2)
TX PCS Latency
(FPGA Fabric-Transceiver
Interface Clock Cycles)
RX PCS Latency
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Figure 1–53
functional mode with a 16-bit PMA-PCS interface.
shows Arria II transceiver configurations allowed in Basic double-width
Figure 1–53
Disabled
1.0 - 4.0
Disabled
11 - 13
62.5 -
16-Bit
250
5 - 6
Manual Alignment
(8-, 16-, 32-Bit)
Disabled
Disabled
is valid only for the -3 (fastest) speed grade devices.
6.5 - 8.5
Disabled
203.125
31.25 -
32-Bit
4 - 5.5
1.0 - 6.375
Enabled
Enabled(2)
6.5 - 8.5
203.125
32-Bit
31.25 -
Disabled
4 - 5.5
Basic Double-Wdith 16-Bit PMA-PCS Interface
Disabled
Disabled
1.0 - 4.0 1.0 - 6.375
11 - 13
16-Bit
62.5 -
(8-, 16-, 32-Bit)
5 - 6
250
Disabled
Disabled
Bit Slip
Chapter 1: Transceiver Architecture in Arria II Devices
1.0 - 6.375 (3)
Device Datasheet for Arria II
×1, ×4, ×8
Disabled
6.5 - 8.5
Enabled
203.125
31.25 -
32-Bit
4 -5.5
Disabled
1.0 - 4.0 1.0 - 6.375
Disabled Disabled
16-Bit
62.5 -
3 - 4
250
4 - 5
Disabled
Disabled
Disabled
Enabled
December 2010 Altera Corporation
Enabled
203.125
3 - 4.5
31.25 -
32-Bit
4 - 5.5
Devices.
Functional Modes