EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 448

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Arria II Device Handbook Volume 2: Transceivers
PCIe Mode
1
Figure 1–61
symbol must be inserted. Because the rate match FIFO can only insert /I2/ ordered
sets, it inserts one /I2/ ordered set (two symbols inserted).
Figure 1–61. Example of Rate Match Insertion in GIGE Mode
The rate match FIFO does not insert or delete code groups automatically to overcome
FIFO empty or full conditions. In this case, the rate match FIFO asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively. You must then assert
the rx_digitalreset signal to reset the receiver PCS blocks.
Intel Corporation has developed a PHY interface for the PCIe architecture
specification to enable implementation of a PCIe-compliant physical layer device.
This specification also defines a standard interface between the physical layer device
and the media access control layer (MAC). Version 2.00 of the specification provides
implementation details for a PCIe-compliant physical layer device at both
Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rates.
Arria II GX and GZ transceivers support ×1, ×4, and ×8 lane configurations in PCIe
functional mode at Gen1 (2.5 Gbps) data rates. Arria II GZ devices also support ×1
and ×4 lane configurations in PCIe functional mode at Gen2 (5.0 Gbps). In PCIe ×1
configuration, the PCS and PMA blocks of each channel are clocked and reset
independently. PCIe ×4 and ×8 configurations support channel bonding for four-lane
and eight-lane PCIe links, where the PCS and PMA blocks of all bonded channels
share common clock and reset signals.
You can configure Arria II GX and GZ transceivers to implement a Version 2.00
PCIe-compliant PHY using one of the following methods:
■
■
PCIe Compiler—This method allows you to use the Arria II GX and GZ devices
built-in PCIe hard IP blocks to implement the PHY-MAC layer, Data Link layer,
and Transaction layer of the PCIe protocol stack. In this mode, each Arria II GX
and GZ transceiver channel uses a PIPE interface block that transfers data, control,
and status signals between the PHY-MAC layer and the transceiver channel PCS
and PMA blocks. The PIPE interface block is used only in this mode and cannot be
bypassed.
ALTGX MegaWizard Plug-In Manager—This method requires implementing the
PHY-MAC layer, Data Link layer, and Transaction layer in the FPGA fabric using a
soft IP. Use this method if you do not use the PCIe hard IP block. (You cannot
access the PCIe hard IP block if you use this method.)
rx_rmfifodatainserted
shows an example of rate match FIFO insertion in the case where one
dataout
datain
Dx.y
Dx.y
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Ordered Set
First /I2/
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Chapter 1: Transceiver Architecture in Arria II Devices
K28.5
K28.5
Ordered Set
Second /I2/
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K28.5
December 2010 Altera Corporation
D16.2
Dx.y
Functional Modes