EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 415

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
Figure 1–30. 10-Bit Deserializer Bit Order
December 2010 Altera Corporation
Low-Speed Parallel Clock
High-Speed Serial Clock
dataout
datain
Deserializer
The deserializer block latches the serial input data from the receiver input buffer with
the high-speed serial recovery clock, deserializes it using the low-speed parallel
recovery clock, and drives the deserialized data to the receiver PCS channel.
The deserializer supports 8-, 10-, 16-, and 20-bit deserialization factors.
shows the deserializer operation with a 10-bit deserialization factor.
Figure 1–29. 10-Bit Deserializer Operation
Figure 1–30
data output of the deserializer block with a 10-bit deserialization factor. The serial
stream (10'b0101111100) is deserialized to a value 10'h17C. The serial data is assumed
to have received the LSB first.
0
0
1
shows the serial bit order of the deserializer block input and the parallel
rx_datain from the input buffer
1
High-Speed Serial Recovery
Low-Speed Parallel Recovery
1
Clock from CDR
Clock from CDR
1
1
0
1
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0101111100
0
Arria II Device Handbook Volume 2: Transceivers
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
10
Figure 1–29
1010000011
1–29