EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 292

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–12
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1
1
If you use the Arria II decompression and/or design security features, the external
host must send a DCLK frequency that is ×4 the data rate.
The ×4 DCLK signal does not require an additional pin and is sent on the DCLK pin. The
maximum DCLK frequency is 125 MHz, which results in a maximum data rate of
250 Mbps. For Arria II GX devices, if you are not using the decompression or design
security features, the data rate is ×1 the DCLK frequency. For Arria II GZ devices, if you
are not using the decompression or design security features, the data rate is ×8 the
DCLK frequency.
Figure 9–1
and a MAX II device for single device configuration.
Figure 9–1. Single Device FPP Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX
(2) You can leave the nCEO pin unconnected or used as a user I/O pin when it does not feed the nCE pin of the other
(3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for
Arria II devices receive configuration data on the DATA[7..0] pins and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If
you are using the Arria II decompression and/or design security features,
configuration data is latched on the rising edge of every fourth DCLK cycle. After the
configuration data is latched in, it is processed during the following three DCLK cycles.
Therefore, you can only stop DCLK after three clock cycles after the last data is latched
into the Arria II device.
In Arria II devices, the initialization clock source is either the internal oscillator or the
optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Arria II device provides itself with
enough clock cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
devices, use the V
V
configuration system I/Os with V
device.
an Arria II GX device, refer to
Table 9–7 on page
IH
specification of the I/O on both the device and the external host. Altera recommends powering up the
Figure
shows the configuration interface connections between an Arria II device
9–1:
(MAX II Device or
Microprocessor)
CCIO
External Host
9–10.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
ADDR DATA[7..0]
pin. For Arria II GZ devices, use the V
Memory
Table 9–6 on page
CCIO
/V
CCPGM
.
V
CCIO
10 kΩ
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
/V
CCPGM
(1)
CCPGM
V
CCIO
10 kΩ
GND
pin. V
/V
CCPGM
CCIO
(1)
/V
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
DATA[7..0]
CCPGM
Arria II Device
December 2010 Altera Corporation
Fast Passive Parallel Configuration
must be high enough to meet the
MSEL[n..0]
nCEO
N.C. (2)
(3)