mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 98

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Exception Processing Overview
2-30
Format Error
Exceptions
Exception
Exception
RTE and
Interrupt
Debug
TRAP
Trace
ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode
(SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor
program execution.
The only exception to this definition is the STOP instruction. If the processor is in trace mode, the
instruction before the STOP executes and then generates a trace exception. In the exception stack
frame, the PC points to the STOP opcode. When the trace handler is exited, the STOP instruction is
executed, loading the SR with the immediate operand from the instruction. The processor then
generates a trace exception. The PC in the exception stack frame points to the instruction after
STOP, and the SR reflects the just-loaded value.
If the processor is not in trace mode and executes a STOP instruction where the immediate operand
sets the trace bit in the SR, hardware loads the SR and generates a trace exception. The PC in the
exception stack frame points to the instruction after STOP, and the SR reflects the just-loaded value.
Because ColdFire processors do not support hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types.
As an example, consider a TRAP instruction executing in trace mode. The processor initiates the
TRAP exception and passes control to the corresponding handler. If the system requires that a trace
exception be processed, the TRAP exception handler must check for this condition (SR[15] in the
exception stack frame asserted) and pass control to the trace handler before returning from the
original exception.
Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the
processor internally calculates the vector number (12). Additionally, the M bit and the interrupt priority
mask fields of the SR are unaffected by the interrupt. See Section 2.2.2.1, “Status Register (SR).”
When an RTE instruction executes, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire processor, any attempted execution of an RTE where the format is not
equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created
without disturbing the original exception frame and the stacked PC points to RTE.The selection of the
format value provides limited debug support for porting code from M68000 applications. On M68000
Family processors, the SR was at the top of the stack. Bit 30 of the longword addressed by the
system stack pointer is typically zero; so, attempting an RTE using this old format generates a format
error on a ColdFire processor.
If the format field defines a valid type, the processor does the following:
1 Reloads the SR operand.
2 Fetches the second longword operand.
3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the first
4 Transfers control to the instruction address defined by the second longword operand in the stack
Executing TRAP always forces an exception and is useful for implementing system calls. The trap
instruction may be used to change from user to supervisor mode.
longword fetch.
frame.
Table 2-21. MCF5
MCF5272 User’s Manual
272
Exceptions (Continued)
Description
MOTOROLA