mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 93

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mcf5272

Manufacturer Part Number
mcf5272
Description
Mcf5272 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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movem.l
MOTOROLA
wdebug.l
Opcode
movem.l
wddata.l
2.7.5 Branch Instruction Execution Times
Table 2-16 shows general branch instruction timing.
Table 2-17 shows timing for Bcc instructions.
trapf.w
Opcode
n is the number of registers moved by the MOVEM opcode.
PEA execution times are the same for (d16,PC).
PEA execution times are the same for (d8,PC,Xi*SF).
The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
pulse
trapf.l
trapf
stop
unlk
nop
pea
trap
jmp
bra
bsr
rte
rts
jsr
1
Table 2-15. Miscellaneous Instruction Execution Times (Continued)
<ea>
<ea>
<ea>
<ea>,&list
&list,<ea>
#imm
#imm
<ea>
<ea>
<ea>
<ea>
Ax
Table 2-16. General Branch Instruction Execution Times
Rn
3(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
2(1/0)
Rn
3(0/0)
3(0/1)
(An)
1+n(n/0)
1+n(0/n)
2(0/1)
3(1/0)
5(2/0)
(An)
Chapter 2. ColdFire Core
10(2/0)
(An)+
5(1/0)
(An)+
3(1/0)
-(An)
Effective Address
3(1/0)
-(An)
Effective Address
(d16,An)
2(0/1)
3(0/1)
3(0/0)
3(0/1)
(d16,An)
1+n(n/0)
1+n(0/n)
2(0/1)
3(1/0)
5(2/0)
2
(d8,An,Xi*SF)
(d8,An,Xi*SF) (xxx).wl
4(0/0)
4(0/1)
3(0/1)
4(1/0)
3
(xxx).wl
Instruction Timing
3(0/0)
3(0/1)
2(0/1)
3(1/0)
#<xxx>
#<xxx>
15(1/2)
3(0/0)
2-25
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