mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 131

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 5-6 describes ABLR fields.
Table 5-7 describes ABHR fields.
5.4.4 Configuration/Status Register (CSR)
The configuration/status register (CSR) defines the debug configuration for the processor
and memory subsystem and contains status information from the breakpoint logic. CSR is
write-only from the programming model. It can be read from and written to through the
BDM port. CSR is accessible in supervisor mode as debug control register 0x00 using the
WDEBUG instruction and through the BDM port using the
commands.
DRc[4–0]
31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
31–0
Bits
Bits
Reset
Field
R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG
Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range.
Name
Name
instruction and via the BDM port using the
ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and
via the BDM port using the
31
Figure 5-6. Address Breakpoint Registers (ABLR, ABHR)
Breakpoints for specific addresses are programmed into ABLR.
Table 5-7. ABHR Field Description
Table 5-6. ABLR Field Description
WDMREG
Chapter 5. Debug Support
command.
0x0D (ABLR); 0x0C (ABHR)
RDMREG
Address
Description
Description
and
—
WDMREG
commands.
RDMREG
Programming Model
and
WDMREG
5-9
0