mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 300

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

GCI/IDL Block
The maximum data rate received for each GCI/IDL port is 144 Kbps: the sum of two
64-Kbps B channels and one 16-Kbps D-channel. Frames of B
together to form longwords (32 bits). Frames of D-channels are packed together to form
bytes. For channels B and D, this requires CPU service at a 2-KHz rate, because it requires
four frames to fill the 32-bit B-channel register and the 8-bit D-channel register.
The CPU should service the B1 and B2 registers once every 500 µS. Overrun conditions
can be avoided only if the CPU services these registers in a timely manner.
The MCF5272 has 4 GCI/IDL interfaces. Thus the theoretical maximum is twelve 32-bit
data registers to be read. For most applications the typical number is less.
Figure 13-3 shows the shift register, shadow register, internal bus register, and multiplexor
for each B receive channel.
After reset, the B- and D-channel shift registers and shadow registers are initialized to all
ones.
13.2.2 GCI/IDL B- and D-Channel Transmit Data Registers
13-4
B1, B2, Receive
Data Register
DCL
Figure 13-3. GCI/IDL B-Channel Receive Data Register Demultiplexing
Dout
Shadow Register
64 Kbps
B1 Shift Register
D
IN
START
B1
32
Figure 13-4. GCI/IDL Transmit Data Flow
8 bits
MCF5272 User’s Manual
B2 Shift Register
Internal Bus
8 bits
Shift Register (B1 or B2)
B2
DEMUX
32 bits
32
8 bits
32
32
8 bits
D Shift Register
2-KHz transfer and interrupt
8-KHz Rate
8 bits
D
1
8
Internal Bus
and B
END
2
Multiplexing
Circuitry
channels are packed
MOTOROLA