mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 365

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
16.3.1 UART Mode Registers 1 (UMR1n)
The UART mode registers 1 (UMR1n) control configuration. UMR1n can be read or
written when the mode register pointer points to it, at RESET or after a
REGISTER POINTER
pointer points to UMR2n.
Table 16-2 describes UMR1n fields.
Bits
4–3
Address
7
6
5
Reset
Field
R/W
RxIRQ/
RxRTS
FFULL
Name
ERR
PM
MBAR + 0x100 (UART0), 0x140 (UART1). After UMR1n is read or written, the pointer points to UMR2n.
RxRTS
7
Receiver request-to-send. Allows the RTS output to control the CTS input of the transmitting device
to prevent receiver overrun. If both the receiver and transmitter are incorrectly programmed for RTS
control, RTS control is disabled for both. Transmitter RTS control is configured in UMR2n[TxRTS].
0 The receiver has no effect on RTS.
1 When a valid start bit is received, RTS is negated if the UART's FIFO is full. RTS is reasserted
If RTS is controlled by the fill level of the receiver FIFO via UACRn[RTSL], this bit should be cleared.
Receiver interrupt select.
0 RxRDY is the source that generates IRQ.
1 FFULL is the source that generates IRQ.
If more detail on the status of the FIFO is required, UISRn{RxFIFO] indicates a change in the FIFO
status as programmed in URFn[RXS].
Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR
1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of
Parity mode. Selects the parity or multidrop mode for the channel. The parity bit is added to the
transmitted character, and the receiver performs a parity check on incoming data. The value of PM
affects PT, as shown below.
when the FIFO has an empty position available.
must be 0 for correct A/D flag information when in multidrop mode.
the FIFO because the last
Section 16.3.5, “UART Command Registers (UCRn).”
RxIRQ/FFULL
command using UCRn[MISC]. After UMR1n is read or written, the
Figure 16-2. UART Mode Registers 1 (UMR1n)
6
Table 16-2. UMR1n Field Descriptions
Chapter 16. UART Modules
ERR
5
RESET ERROR STATUS
4
0000_0000
Description
R/W
PM
command for the channel was issued. See
3
PT
2
Register Descriptions
1
RESET MODE
B/C
0
16-5