mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 187

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
If the core initiates an interrupt acknowledge cycle prior to the PIVR being programmed,
the interrupt controller returns the uninitialized interrupt vector (0x0F). If the core initiates
an interrupt acknowledge cycle after the PIVR has been initialized, but there is no interrupt
pending, the interrupt controller returns the user a spurious interrupt vector (0xxxx0_0000).
Because the interrupt controller responds to all interrupt acknowledges, a bus error situation
cannot occur during an interrupt-acknowledge cycle.
Table 7-7 describes PIVR fields.
Table 7-8 lists the values for the five least significant bits of the interrupt vector. The vector
numbers shown assume PIVR[IV]=0b010. If another value of PIVR[IV] is used, the vector
numbers would change accordingly.
Bits
7-5
4-0
Vector Number
Field
IV
—
64
65
66
67
68
69
70
71
72
73
74
75
Address
Reset
Field
R/W
These bits provide the high three bits of the interrupt vector for interrupt acknowledge cycles from all
sources. To conform to the core interrupt vector allocation, these bits should be set equal to or greater
than 010. See Table 2-3.
Reserved, should be cleared.
Figure 7-9. Programmable Interrupt Vector Register (PIVR)
7
Table 7-8. MCF5272 Interrupt Vector Table
Bits 4–0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
Table 7-7. PIVR Field Descriptions
IV
Chapter 7. Interrupt Controller
5
Reserved
Source
UART1
UART2
TMR0
TMR1
TMR2
TMR3
INT1
INT2
INT3
INT4
PLIP
MBAR + 0x03F
4
0000_1111
Description
R/W
External Interrupt Input 1
External Interrupt Input 2
External Interrupt Input 3
External Interrupt Input 4
—
User Spurious Interrupt
PLIC 2KHz Periodic
Interrupt Controller Registers
Function
Timer 0
Timer 1
Timer 2
Timer 3
UART 1
UART 2
0
7-9