mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 348

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
Table 14-3 gives QMR field descriptions.
Figure 14-4 shows an example of a QSPI clocking and data transfer.
14-10
13–10
Bits
7–0
15
14
9
8
DOHIE
Name
MSTR
CPOL
CPHA
BAUD
BITS
Master mode enable.
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.
Data output high impedance enable. Selects QSPI_Dout mode of operation.
0 Default value after reset. QSPI_Dout is actively driven between transfers.
1 QSPI_Dout is high impedance between transfers.
Transfer size. Determines the number of bits to be transferred for each entry in the queue.
Value
0000
0001– 0111
1000
1001
1010
1011
1100
1101
1110
1111
Clock polarity. Defines the clock polarity of SCK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of
Baud rate divider. The baud rate is selected by writing 0, or a value in the range 2–255. 1 is not a
valid value. A value of zero disables the QSPI. The desired QSPI_CLK baud rate is related to
CLKIN and QMR[BAUD] by the following expression:
QSPI_CLK.
QSPI_CLK.
QMR[BAUD] = SystemClock / [2 × (desired QSPI_CLK baud rate)]
Table 14-3. QMR Field Descriptions
Bits per transfer
16
10
11
12
13
14
15
Reserved
8
9
MCF5272 User’s Manual
Description
MOTOROLA