mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 95

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address
boundary; see Table 2-18. The table contains 256 exception vectors where the first 64 are
defined by Motorola; the remaining 192 are user-defined interrupt vectors.
ColdFire processors inhibit sampling for interrupts during the first instruction of all
exception handlers. This allows any handler to effectively disable interrupts, if necessary,
by raising the interrupt mask level contained in the status register.
1
Vector Numbers
The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC
of the instruction that immediately follows the instruction that caused the fault.
64–255
16–23
25–31
32–47
48–60
62–63
4 x vector_number. When the index value is generated, the vector table contents
determine the address of the first instruction of the desired handler. After the fetch
of the first opcode of the handler is initiated, exception processing terminates and
normal instruction processing continues in the handler.
6–7
10
11
12
13
14
15
24
61
0
1
2
3
4
5
8
9
Vector Offset (Hex)
080–0BC
0C0–0F0
0F8–0FC
100–3FC
Table 2-18. Exception Vector Assignments
018–01C
040–05C
064–07C
00C
02C
03C
0F4
000
004
008
010
014
020
024
028
030
034
038
060
Chapter 2. ColdFire Core
Stacked Program Counter
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Next
Next
Next
Next
Next
Next
Next
—
—
—
—
—
—
—
1
Initial stack pointer
Initial program counter
Access error
Address error
Illegal instruction
Divide by zero
Reserved
Privilege violation
Trace
Unimplemented line-a opcode
Unimplemented line-f opcode
Debug interrupt
Reserved
Format error
Uninitialized interrupt
Reserved
Spurious interrupt
Level 1–7 autovectored interrupts
Trap #0–15 instructions
Reserved
Unsupported instruction
Reserved
User-defined interrupts
Exception Processing Overview
Assignment
2-27