mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 483

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Chapter 21
IEEE 1149.1 Test Access Port (JTAG)
This chapter describes the dedicated user-accessible test logic implemented on the
MCF5272. This test logic complies fully with the IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture. This chapter describes those items required by the
standard and provides additional information specific to the MCF5272 implementation. For
internal details and sample applications, see the IEEE 1149.1 document.
21.1 Overview
Problems with testing high-density circuit boards led to development of this standard under
the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group
(JTAG). The MCF5272 supports circuit board test strategies based on this standard.
The test logic includes a test access port (TAP) consisting a 16-state controller, an
instruction register, and three test registers (a 1-bit bypass register, a 265-bit boundary-scan
register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. The contents of this register can be found at the ColdFire website at
http://www.motorola.com/semiconductors. Test logic, implemented using static logic
design, is independent of the device system logic. The TAP includes the following
dedicated signals:
These signals, described in detail in Table 21-1, are enabled by negating the Motorola test
mode signal (MTMOD).
• TCK—Test clock input to synchronize the test logic.
• TMS—Test mode select input (with an internal pullup resistor) that is sampled on
• TDI—Test data input (with an internal pull-up resistor) that is sampled on the rising
• TDO—three-state test data output that is actively driven in the shift-IR and shift-DR
the rising edge of TCK to sequence the TAP controller's state machine.
edge of TCK.
controller states. TDO changes on the falling edge of TCK.
Chapter 21. IEEE 1149.1 Test Access Port (JTAG)
21-1