mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 359

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
15.3.3 Timer Capture Registers (TCAP0–TCAP3)
Each TCAP is used to latch the TCN value during a capture operation when an edge occurs
on the respective TIN0, TIN1, UART0_RxD, or UART1_RxD, as programmed in TMRn.
15.3.4 Timer Counters (TCN0–TCN3)
TCN registers are 16-bit up counters. Reading a TCNn gives the current counter value
without affecting counting. A write cycle to a TCN register causes it to be cleared.
15.3.5 Timer Event Registers (TER0–TER3)
TERs are used to report events recognized by the timer. On recognition of an event, the
timer sets the appropriate TERn bit, regardless of the corresponding interrupt enable bits
(ORI and CE) in the TMRn. Writing a 1 to a bit clears it; writing 0 has no effect. Both bits
must be cleared before the timer can negate the request to the interrupt controller. Both bits
may be cleared simultaneously.
Table 15-2 describes TERn fields.
Reset
Reset
Reset
Field
Field
Field
Addr
Addr
Addr
R/W
R/W
R/W
15
15
15
Figure 15-4. Timer Capture Registers (TCAP0–TCAP3)
Figure 15-6. Timer Event Registers (TER0–TER3)
MBAR + 0x200 (TCAP0); 0x220 (TCAP1); 0x240 (TCAP2); 0x260 (TCAP3)
MBAR + 0x20C (TCN0); 0x22C (TCN1); 0x24C (TCN2); 0x26C (TCN3)
MBAR + 0x210 (TER0); 0x230 (TER1); 0x250 (TER2); 0x270 (TER3)
Figure 15-5. Timer Counter (TCN0–TCN3)
Chapter 15. Timer Module
COUNT (16-bit timer counter value)
CAP (16-bit capture counter value)
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
—
Read/Write
Read/Write
Read Only
General-Purpose Timer Registers
2
REF CAP
1
15-5
0
0
0