mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 320

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

PLIC Registers
13.5.11 Aperiodic Status Register (PASR)
All bits in this register are read only and are set on hardware or software reset.
The PASR register is a 16-bit register containing the aperiodic interrupt status information
for the C/I and monitor channel transmit and receive registers for all four ports on the
MCF5272. An aperiodic interrupt condition remains asserted as long as any one of the bits
within the PASR register is set.
13.5.12 GCI Monitor Channel Receive Registers
All bits in these registers are read only and are initialized to 0x00FF on hardware or
software reset.
PnGMR are 16-bit registers containing the received monitor channel bits for each of the
four receive ports on the MCF5272.
13-24
Reset
Field GCR
Addr
R/W
15, 11, 7, 3
14, 10, 6, 2
13, 9, 5, 1
12, 8, 4, 0
Bits
15
3
(P0GMR–P3GMR)
GCT
14
3
GMRn
Name
GCRn
GMTn
GCTn
GMR
13
3
Figure 13-23. Aperiodic Status Register (PASR)
GMT
12
3
GCI C/I received. When set, this bit indicates that valid new data has been written to
a GCI C/I receive register. An interrupt is queued when this bit is set if the GCR
interrupt enable bit has been set in the corresponding PnICR register. The GCR bit
and associated interrupt are automatically cleared when the corresponding PnGCIR
register has been read by the CPU.
GCI C/I transmitted. When set, this bit indicates that a C/I register is empty. An
interrupt is queued when this bit is set if the GCT interrupt enable bit has been set in
the corresponding PnICR register. The GCT bit and associated interrupt are
automatically cleared when the PGCITSR register has been read by the CPU.
GCI monitor received. When set, this bit indicates that data has been written to a
monitor channel receive register. An interrupt is queued when this bit is set if the
GMR interrupt enable bit has been set in the corresponding PnICR register. The
GMR bit and associated interrupt are automatically cleared when the corresponding
PnGMR register has been read by the CPU.
GCI monitor transmitted. When set, this bit indicates that the monitor channel
transmit register is empty. An interrupt is queued when this bit is set if the GMT
interrupt enable bit has been set in the corresponding PnICR register. The GMT bit
and associated interrupt are automatically cleared when the PGMTS register has
been read by the CPU.
Table 13-6. PASR Field Descriptions
GCR
11
2
GCT
10
2
MCF5272 User’s Manual
GMR
0000_0000_0000_0000
2
9
MBAR + 0x38C
GMT
Read Only
8
2
GCR
7
1
Description
GCT
1
6
GMR
1
5
GMT
1
4
GCR
0
3
GCT
0
2
MOTOROLA
GMR
1
0
GMT
0
0