mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 112

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

ROM Overview
4.4.2 ROM Programming Model
The MCF5272 implements the ROM base address register (ROMBAR), shown in
Figure 4-2 and described in the following section.
4.4.2.1 ROM Base Address Register (ROMBAR)
ROMBAR determines the base address location of the internal ROM module, as well as the
definition of the allowable access types. ROMBAR can be accessed in supervisor mode
using the MOVEC instruction with an Rc value of 0xC00. It can also be read when the
processor is in background debug mode (BDM). To access the ROM module, ROMBAR
should be initialized with the appropriate base address.
ROMBAR fields are described in Table 4-4.
Address
4-6
31–14
13–6
Bits
5–1
Reset
0
Field
R/W
Name
31
SC,
SD,
UC,
C/I,
UD
BA
—
V
Base address. Defines the ROM module base address. ROM can reside on any 4-Kbyte boundary
in the 4-Gbyte address space.
Reserved, should be cleared.
Address space masks (ASn). Allows specific address spaces to be enabled or disabled, placing
internal modules in a specific address space. If an address space is disabled, an access to the
register in that address space becomes an external bus access, and the module resource is not
accessed. These bits are useful for power management as described in Section 4.4.2.2,
“Programming ROMBAR for Power Management.” In particular, C/I is typically set.
The address space mask bits are follows:
C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each ASn bit:
0 An access to the ROM module can occur for this address space
1 Disable this address space from the ROM module. References to this address space cannot
Valid. Indicates whether ROMBAR contents are valid. The BA value is not used and the ROM
module is not accessible until V is set.
0 Contents of ROMBAR are not valid.
1 Contents of ROMBAR are valid.
access the ROM module and are processed like other non-ROM references.
Figure 4-2. ROM Base Address Register (ROMBAR)
BA
Table 4-4. ROMBAR Field Description
—
MCF5272 User’s Manual
W for CPU; R/W for debug
CPU space + 0xC00
14
13
Description
—
8
7
00
—
6
C/I SC SD UC UD
—
5
—
4
—
3
MOTOROLA
—
2
—
1
V
0
0