mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 249

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 11-22 describes the TCR fields.
11.5.16 RAM Perfect Match Address Low (MALR)
The MALR register contains the lower 32 bits of the 48 bit MAC address used in the
address recognition process to compare with the Destination Address field of the receive
frames.
This register, shown in Figure 11-19, is not reset and must be initialized by the user prior
to operation.
Reset
Reset
Field
Field
31–3
Addr
R/W
R/W
Bits
2
1
0
31
15
Name
FDEN
HBC
GTS
—
Reserved, should be cleared.
Full duplex enable. If set, frames are transmitted independent of carrier sense and collision
inputs. This bit should only be modified when ETHER_EN is deasserted.
Heartbeat control. If set, the heartbeat check is performed following end of transmission and
the HB bit in the status register is set if the collision input does not assert within the heartbeat
window. This bit should be modified only when ETHER_EN is deasserted.
Graceful transmit stop. When this bit is set, the MAC stops transmission after any current
frame is complete and the GRA interrupt in the INTR_EVENT register is asserted. If frame
transmission is not currently underway, the GRA interrupt is asserted immediately. Once
transmission is complete, a restart is accomplished by clearing the GTS bit. The next frame in
the transmit FIFO is then transmitted. If an early collision occurs during transmission when
GTS = 1, transmission stops after the collision. The frame is transmitted again once GTS is
cleared. Note that there may be old frames in the transmit FIFO that are transmitted when
GTS is reasserted. To avoid this, deassert ETHER_EN following the GRA interrupt.
Figure 11-18. Transmit Control Register (TCR)
Table 11-22. TCR Field Descriptions
Chapter 11. Ethernet Module
—
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x984
Read/Write
Read/Write
—
Description
3
Programming Model
FDEN HBC GTS
2
1
11-25
16
0