mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 275

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 12-11 lists field descriptions for the IEP0CFG register. Only longword writes are
allowed. The maximum packet size for endpoint 0 is eight bytes. Writing to the register
resets the FIFO. Any data in the FIFO are discarded, and the associated EPnDP register is
also reset.
12.3.2.11 USB Endpoint 0 OUT Configuration Register (OEP0CFG)
Figure 12-14 shows the USB endpoint 0 OUT configuration register.
31–22 MAX_PACKET Maximum packet size. Must be written with the maximum packet size defined in the device
20–11
Bits
9–0
Reset
Reset
21
10
Field
Field
Addr
R/W
R/W
Reset
Reset
Field
Field
Addr
R/W
R/W
FIFO_ADDR
Figure 12-13. USB Endpoint 0 IN Configuration Register (IEP0CFG)
FIFO_SIZE
31
15
31
15
Name
—
—
Figure 12-14. USB Endpoint 0 OUT Configuration Register
FIFO_SIZE
FIFO_SIZE
descriptor for endpoint 0 or the endpoint descriptors for other endpoints.
Reserved, should be cleared.
Size of the FIFO. Sets the depth of the FIFO buffer for the endpoint. The FIFO size must be
a power of 2. For non-isochronous endpoints, the FIFO size must be at least two times the
maximum packet size.
Reserved, should be cleared.
Starting address in the FIFO buffer memory for the endpoint’s FIFO. Reading this field
returns the current write pointer for IN endpoints or the read pointer for OUT endpoints for
the FIFO.
Table 12-11. IEP0CFG Field Descriptions
Chapter 12. Universal Serial Bus (USB)
MAX_PACKET
MAX_PACKET
11
11
10
—
—
10
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
9
9
MBAR + 0x102C
MBAR + 0x1028
R/W
R/W
R/W
R/W
Register Description and Programming Model
Descriptions
22
22
FIFO_ADDR
FIFO_ADDR
—
21
—
21
20
20
FIFO_SIZE
FIFO_SIZE
12-15
16
0
16
0