mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 489

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
21.5 Instruction Register
The MCF5272 IEEE 1149.1 implementation includes the three mandatory public
instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), the optional public ID
instruction, plus two additional public instructions (CLAMP and HI-Z) defined by IEEE
1149.1. The MCF5272 includes a 4-bit instruction register without parity, consisting of a
shift register with four parallel outputs. Data is transferred from the shift register to the
parallel outputs during the update-IR controller state. The 4 bits are used to decode the
instructions in Table 21-2.
The parallel output of the instruction register is reset to 0001 in the test-logic-reset
controller state. Note that this preset state is equivalent to the ID instruction.
B[3:0] Instruction
0000
0001
EXTEST
ID
NOTE: More than one lO.Cell could be serially connected and controlled by a single En.Cell.
Figure 21-7. General Arrangement for Bidirectional Pins
INPUT
The external test (EXTEST) instruction selects the boundary scan register. EXTEST asserts
internal reset for the MCF5272 system logic to force a predictable benign internal state while
performing external boundary scan operations.
By using the TAP, the register is capable of a) scanning user-defined values into the output
buffers, b) capturing values presented to input pins, c) controlling the direction of bidirectional
pins, and d) controlling the output drive of three-state output pins. For more details on the
function and uses of EXTEST, please refer to the IEEE 1149.1 document.
During the capture-IR controller state, the parallel inputs to the instruction shift register are
loaded with the 4-bit binary value (0001). The parallel outputs, however, remain unchanged
by this action since an update-IR signal is required to modify them.
DATA
O
E
O
Chapter 21. IEEE 1149.1 Test Access Port (JTAG)
Table 21-2. Instructions
FROM LAST CEL
TO NEXT CEL
EN.CELL
IO.CELL
*
*
DIRECTION
Description
OUTPUT
ENABLE
Instruction Register
I/O
PIN
21-7