mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 116

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Instruction Cache Overview
if (address == ACR0-address including mask)
else if (address == ACR1-address including mask)
Addresses matching an ACR can also be write-protected using ACR[WP].
Reset disables the cache and clears all CACR bits. Reset does not automatically invalidate
cache entries; they must be invalidated through software.
The ACRs allow CACR defaults to be overridden. In addition, some instructions (for
example, CPUSHL) and processor core operations perform accesses that have an implicit
caching mode associated with them. The following sections discuss the different caching
accesses and their associated cache modes.
4.5.2.3.1 Cacheable Accesses
If ACRn[CM] or the default field of the CACR indicates the access is cacheable, a read
access is read from the cache if matching data is found. Otherwise, the data is read from
memory and the cache is updated. When a line is being read from memory, the longword
in the line that contains the core-requested data is loaded first and the requested data is
given immediately to the processor, without waiting for the three remaining longwords to
reach the cache.
4.5.2.3.2 Cache-Inhibited Accesses
Memory regions can be designated as cache-inhibited, which is useful for memory
containing targets such as I/O devices and shared data structures in multiprocessing
systems. Do not cache memory-mapped registers (for example, registers shown with an
MBAR offset). If the corresponding ACRn[CM] or CACR[DCM] indicates cache-inhibited
the access is cache-inhibited. The caching operation is identical for both cache-inhibited
modes, which differ only regarding recovery from an external bus error.
In determining whether a memory location is cacheable or cache-inhibited, the CPU checks
memory-control registers using the following priority:
Cache-inhibited write accesses bypass the cache and a corresponding external write is
performed. Cache-inhibited reads bypass the cache and are performed on the external bus,
except when all of the following conditions are true:
4-10
1. RAMBAR
2. ROMBAR
3. ACR0
4. ACR1
5. If an access does not hit in RAMBAR, ROMBAR, or the ACRs, the default is
provided for all accesses in CACR.
effective attributes = ACR0 attributes
else effective attributes = CACR default attributes
effective attributes = ACR1 attributes
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