mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 302

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

GCI/IDL Block
frame in the most significant byte (MSB) position, and the fourth frame taking the least
significant byte (LSB) position. See Section 13.5.1, “B1 Data Receive Registers
(P0B1RR–P3B1RR),”
(P0B2TR–P3B2TR),” for more information about some of these registers.
13.2.3.2 B-Channel HDLC Encoded Data
When the incoming B channels contain HDLC encoded data they are presented on the
physical line least significant bit (lsb) first. The Soft HDLC expects the first bit received to
be aligned in the lsb position of a byte, with the last bit received aligned in the msb position.
Because the presentation of HDLC encoded data on the physical interface is lsb (least
significant bit) first for B1 and B2 the lsb is right-aligned in the transmit and receive shift
register, that is, the first bit of the B-channel received is aligned in the lsb position through
to the last received bit of a byte that is aligned in the msb position.
The ordering of the bytes over four frames within the longword register is as for unencoded
data; that is, the first frame is aligned in the MSB through to the fourth frame, which is
aligned in the LSB position. See Figure 13-6.
13-6
Unencoded
.
HDLC
Encoded
32-bit B1/B2 Receive/Transmit Registers, PnB1RR, PnB2RR, PnB1TR, PnB2TR
Din/Dout
Din/Dout
B
7
DCL
FSR
B
6
B
5
Frame 0
Figure 13-6. B-Channel Unencoded and HDLC Encoded Data
B
4
B
B
B
3
7
0
B
B
B
2
6
1
B
B
B
1
5
2
B
B
B
4
3
0
B 1
B
B
B
or
3
4
7
B
B
B
2
5
6
B
B
B
1
6
5
Section 13.5.5,
Frame 1
B
B
B
0
7
Frame 0
4
MCF5272 User’s Manual
B
B
B
7
0
3
B
B
1
B
6
B
2
B
5
2
B
B
B
1
4
3
B
B 2
B
B
0
4
3
B
B
B
7
5
2
B
B
B
6
1
6
“B2
B
B
B
5
0
7
Frame 2
D
D
B
0
0
4
D
D
D
B
1
1
3
Data
B
2
B
1
B
0
B
Transmit
7
B
6
B
Frame 3
5
B
B
7
0
B
4
B
B
6
1
Frame 1
B
B
B
3
MOTOROLA
5
2
B
Registers
B
B
2
4
3
B
B
B
1
3
4
B
B
B
0
2
5