mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 115

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
4.5.2 Instruction Cache Operation
The instruction cache is physically connected to the ColdFire core's local bus, allowing it
to service all instruction fetches from the ColdFire core and certain memory fetches
initiated by the debug module. Typically, the debug module's memory references appear as
supervisor data accesses but the unit can be programmed to generate user-mode accesses
and/or instruction fetches. The instruction cache processes any instruction fetch access in
the normal manner.
4.5.2.1 Interaction with Other Modules
Because both the instruction cache and high-speed SRAM module are connected to the
ColdFire core's local data bus, certain user-defined configurations can result in
simultaneous instruction fetch processing.
If the referenced address is mapped into the SRAM module, that module services the
request in a single cycle. In this case, data accessed from the instruction cache is discarded
without generating external memory references. If the address is not mapped into SRAM
space, the instruction cache handles the request in the normal fashion.
4.5.2.2 Cache Coherency and Invalidation
The instruction cache does not monitor ColdFire core data references for accesses to cached
instructions. Therefore, software must maintain cache coherency by invalidating the
appropriate cache entries after modifying code segments.
Cache invalidation can be performed in the two following ways:
These invalidation operations can be initiated from the ColdFire core or the debug module.
4.5.2.3 Caching Modes
For every memory reference generated by the processor or debug module, a set of effective
attributes is determined based on the address and the ACRs. Caching modes determine how
the cache handles an access. An access can be cacheable or cache-inhibited. For normal
accesses, the ACRn[CM] bit corresponding to the address of the access specifies the
caching mode. If an address does not match an ACR, the default caching mode is defined
by CACR[DCM]. The specific algorithm is as follows:
• Setting CACR[CINVA] forces the entire instruction cache to be marked as invalid.
• The privileged CPUSHL instruction can invalidate a single cache line. When this
The invalidation operation requires 64 cycles because the cache sequences through
the entire tag array, clearing a single location each cycle. Any subsequent instruction
fetch accesses are postponed until the invalidation sequence is complete.
instruction is executed, the cache entry defined by bits 9–4 of the source address
register is invalidated, provided CACR[CDPI] is cleared.
Chapter 4. Local Memory
Instruction Cache Overview
4-9