mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 445

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
19.15.5 Synchronous Peripheral Chip Select 1
See Section 19.16.1.9, “QSPI Chip Select 1 (QSPI_CS1/PA11).”
QSPI_CS1 can be programmed to be active high or low.
19.15.6 Synchronous Peripheral Chip Select 2
See Section 19.16.1.5, “UART1 CTS (URT1_CTS/QSPI_CS2).”
19.15.7 Synchronous Peripheral Chip Select 3
See
(PA7/DOUT3/QSPI_CS3).” See description for GPIO ports.
19.16 Physical Layer Interface Controller TDM Ports
The MCF5272 has four dedicated physical layer interface ports for connecting to external
ISDN transceivers, CODECs and other peripherals. There are three sets of pins for these
interfaces. Port 0 has its own dedicated set of pins. Ports 1, 2, and 3 share a set of pins.
Port 3 can also be configured to use a dedicated pin set. Ports 1, 2, and 3 always share the
same data clock (DCL).
19.16.1 GCI/IDL TDM Port 0.
This section describes signals used by the PLIC module port 0 interface.
19.16.1.1 Frame Sync (FSR0/FSC0/PA8)
IDL mode: FSR0 is an input for the 8-KHz frame sync for port 0.
GCI mode: FSC0 is an input for the 8-KHz frame sync for port 0. It is active high in this
mode. Normally the GCI FSC signal is two clocks wide and is aligned with the first
B-channel bit of the GCI frame. Many U-interface devices including the MC145572 and
MC145576 change the width of FSC to one clock every 12 mS. This indicates U-interface
super frame boundary.
Port A mode: This pin can be independently configured as PA8.
Section 19.16.3.3,
and UART 1
(QSPI_CS1/PA11)
(QSPI_CS2/URT1_CTS)
(PA7/DOUT3/QSPI_CS3)
“QSPI_CS3,
Chapter 19. Signal Descriptions
Physical Layer Interface Controller TDM Ports and UART 1
Port
3
GCI/IDL
Data
Out
3,
19-31
PA7