mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 459

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
20.5.1 Bus Sizing
The MCF5272 can be configured for an external physical data bus width of 16 bits by
pulling QSPI_Dout/WSEL high, or for 32 bits by pulling QSPI_Dout/WSEL low during
reset. When the external physical address bus size is configured for 16 bits, the signals
D[15:0] become general purpose I/O port C.
The MCF5272 determines the port size for each transfer from the CSBRs at the start of each
bus cycle. This allows the MCF5272 to transfer operands from 8-, 16-, or 32-bit ports. The
size of the transfer is adjusted to accommodate the port size indicated. A 32-bit port must
reside on data bus bits D[31:0], a 16-bit port must reside on data bus bits D[31:16], and an
8-bit port must reside on data bus bits D[31:24]. This requirement ensures that the
MCF5272 correctly transfers valid data to 8-, 16-, and 32-bit ports.
The bytes of operands are designated as shown in Figure 20-1. The most significant byte of
a longword operand is OP0; OP3 is the least significant byte. The two bytes of a word length
operand are OP2 (most significant) and OP3. The single byte of a byte length operand is
OP3. These designations are used in the figures and descriptions that follow.
Figure 20-2 shows the required organization of data ports on the MCF5272 for 8-, 16-, and
32 bit devices. The four bytes shown are connected through the internal data bus and data
multiplexer to the external data bus. This path is how the MCF5272 supports programmable
port sizing and operand misalignment. The data multiplexer establishes the necessary
connections for different combinations of address and data sizes.
Table 20-2. Chip Select Memory Address Decoding Priority (Continued)
31
OP0
Figure 20-1. Internal Operand Representation
OP1
Priority
Chapter 20. Bus Operation
Lowest
15
OP2
OP2
7
Chip Select 3
Chip Select 4
Chip Select 5
Chip Select 6
Chip Select 7
OP3
OP3
Chip Select
OP3
0
0
0
LONGWORD OPERAND
BYTE OPERAND
WORD OPERAND
Data Transfer Mechanism
20-5