mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 69

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Chapter 2
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF5272. The
chapter describes the V2 programming model as it is implemented on the MCF5272. It also
includes a full description of exception handling, data formats, an instruction set summary,
and a table of instruction timings.
2.1 Features and Enhancements
The MCF5272 is the most highly-integrated V2 standard product, containing a variety of
communications and general-purpose peripherals. The V2 core was designed to maximize
code density and performance while minimizing die area.
The following list summarizes MCF5272 features:
2.1.1 Decoupled Pipelines
The IFP prefetches instructions. The OEP decodes instructions, fetches required operands,
then executes the specified function. The two independent, decoupled pipeline structures
maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1
and are summarized as follows:
• Variable-length RISC Version 2 microprocessor core
• Two independent, decoupled pipelines—two-stage instruction fetch pipeline (IFP)
• Three longword FIFO buffer provides decoupling between the pipelines
• 32-bit internal address bus supporting 4 Gbytes of linear address space
• 32-bit data bus
• 16 user-accessible, 32-bit-wide, general-purpose registers
• Supervisor/user modes for system protection
• Vector base register to relocate exception-vector table
• Optimized for high-level language constructs
and two-stage operand execution pipeline (OEP)
Chapter 2. ColdFire Core
2-1