mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 111

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
4.3.2.3 Programming RAMBAR for Power Management
Depending on the configuration defined by RAMBAR, instruction fetch accesses can be
sent to the SRAM module, ROM module, and instruction cache simultaneously. If the
access is mapped to the SRAM module, it sources the read data, discarding the instruction
cache access. If the SRAM is used only for data operands, setting RAMBAR[SC,UC]
lowers power dissipation by disabling the SRAM during all instruction fetches.
Additionally, if the SRAM holds only instructions, setting RAMBAR[SD,UD] reduces
power dissipation.
Consider the examples on Table 4-3 of typical RAMBAR settings:
ROMBAR can be configured similarly, as described in Section 4.4.2.2, “Programming
ROMBAR for Power Management.”
4.4 ROM Overview
The ROM modules has the following features:
4.4.1 ROM Operation
The ROM module contains tabular data that the ColdFire core can access in a single cycle.
The ROM can be located on any 16-Kbyte address boundary in the 4-Gbyte address space.
Section 4.1, “Interactions between Local Memory Modules,” describes priorities when a
fetch address hits multiple local memory resources.
• 16-Kbyte ROM, organized as 4K x 32 bits
• Contains data tables for soft HDLC (high-level data link control)
• The ROM contents are not customizeable
• Single-cycle access
• Physically located on ColdFire core's high-speed local bus
• Byte, word, longword address capabilities
• Programmable memory mapping
Table 4-3. Examples of Typical RAMBAR Settings
Instructions only
Data only
Both instructions and data
Data Contained in SRAM RAMBAR[7–0]
Chapter 4. Local Memory
0x2B
0x35
0x21
ROM Overview
4-5