mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 230

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

FEC Frame Transmission
When the FEC receiver is enabled by setting ECR[ETHER_EN] and RDAR[24] it
immediately starts processing receive frames. Received frame processing proceeds as
follows:
As soon as a collision window (512 bits) of data is received, and if address recognition has
not rejected the frame, the FEC starts transferring the incoming frame to the receive buffer
descriptor’s (RxBD’s) associated data buffer. If the frame is a runt (due to collision) or is
rejected by address recognition, no receive buffers are filled. Thus, no collision frames are
presented to the user except late collisions, which indicate serious LAN problems. When
the data buffer has been filled, the FEC clears RxBD[E] and generates an RXB interrupt (if
RBIEN is asserted in EIMR register). If the incoming frame exceeds the length of the data
buffer, the FEC fetches the next RxBD in the table and, if it is empty, continues transferring
the rest of the frame to this BD’s associated data buffer.
The RxBD length is determined in the R_BUFF_SIZE value in the EMRBR register. The
user should program R_BUFF_SIZE to be at least 128 bytes. R_BUFF_SIZE must be
quad-word (16-byte) aligned.
During reception, the FEC checks for a frame that is either too short or too long. When the
frame ends (carrier sense is negated), the receive CRC field is checked and written to the
data buffer. The data length written to the last BD in the Ethernet frame is the length of the
entire frame. Frames shorter than 64 bytes are discarded automatically with no system bus
impact.
When the receive frame is complete, the FEC sets RxBD[L], writes the other frame status
bits into the RxBD and clears RxBD[E]. The FEC next generates a maskable interrupt
11-6
• When E_RxDV asserts, the receiver first checks for a valid header comprised of a
• If the PA/SFD is valid, it is stripped off and the frame processed further by the
• In serial mode, the first 16 bit times of E_RxD0 following assertion of E_RxDV
• After the first 16 bit times, the data sequence is checked for alternating I/0.
• If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the
• After bit time 21, the data sequence is monitored for a valid start-of-frame delimiter
• In MII mode, the receiver checks for at least one byte matching the SFD. Zero or
• After the first 8 bytes of the frame have been passed to the receive FIFO, the FEC
preamble and start-of-frame delimiter (PA/SDF).
receiver. If a valid PA/SFD is not found, the frame is ignored.
(RENA) are ignored.
frame is ignored.
(SFD) of 11. If a 00 is detected, the frame is rejected. When a 11 is detected, the
PA/SFD sequence is complete.
more PA bytes may occur, but if a 00 bit sequence is detected before the SFD byte,
the frame is ignored.
performs address recognition on the frame.
MCF5272 User’s Manual
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