mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 158

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Real-Time Debug Support
5.6.1.1 Emulator Mode
Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be
entered in three different ways:
While operating in emulation mode, the processor exhibits the following properties:
The RTE instruction exits emulation mode. The processor status output port provides a
unique encoding for emulator mode entry (0xD) and exit (0x7).
5.6.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM
commands. BDM commands may be executed while the processor is running, except those
following operations that access processor/memory registers:
For BDM commands that access memory, the debug module requests the processor’s local
bus. The processor responds by stalling the instruction fetch pipeline and waiting for
current bus activity to complete before freeing the local bus for the debug module to
perform its access. After the debug module bus cycle, the processor reclaims the bus.
Breakpoint registers must be carefully configured in a development system if the processor
is executing. The debug module contains no hardware interlocks, so TDR should be
disabled while breakpoint registers are loaded, after which TDR can be written to define the
exact trigger. This prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed
while the CPU is writing the debug’s registers (DSCLK must be inactive).
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• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined
• A debug interrupt always puts the processor in emulation mode when debug
• Setting CSR[TRC] forces the processor into emulation mode when trace exception
• All interrupts are ignored, including level-7 interrupts.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All
• Read/write address and data registers
• Read/write control registers
only if RSTI is negated and the processor begins reset exception processing. It can
be set while the processor is halted before reset exception processing begins. See
Section 5.5.1, “CPU Halt.”
interrupt exception processing begins.
processing begins.
memory accesses are forced into a specially mapped address space signaled by
TT = 0x2, TM = 0x5 or 0x6. This includes stack frame writes and the vector fetch
for the exception that forced entry into this mode.
MCF5272 User’s Manual
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