mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 196

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

SDRAM Controller Signals
Figure 9-1 shows the SDRAM controller signal configuration.
Table 9-1 describes SDRAM controller signals.
9-2
Internal 32-Bit Address Bus
A10_PRECHG
DRESETEN
SDA[13:0]/
SDBA[1:0]
BS[3:0]
A[22:0]
Signal
CAS0
RAS0
A10 precharge strobe. A precharge cycle occurs only after a page miss. During precharge, the
SDRAM writes the designated on-chip RAM page buffer back into the SDRAM array.
Precharge latency is set in SDTR[RP]. The reset value is 2 cycles, RP = 01.
For SDRAM devices, these outputs should be connected to individual DQM signals. During
SDRAM accesses, these signals indicate a byte transfer between SDRAM and the MCF5272
when asserted. Note that most SDRAMs associate DQM3 with the MSB, in which case BS3
should be connected to the SDRAM's DQM3 input, and so forth.
SDRAM column address strobe output
DRESETEN is asserted to indicate that the SDRAM controller is to be reset whenever RSTI
asserts. If DRESETEN is negated, RSTI does not affect the SDRAM controller, which
continues to refresh external memory. This is useful for debug situations where a reset of the
device is required without losing data located in SDRAM. DRESETEN is normally tied high or
low depending on system requirements. It should never be tied to RSTI or RSTO.
SDRAM row address strobe output
Fourteen address signals are multiplexed to form SDRAM_ADR[13:0], which are used for
connecting to SDRAM devices as large as 256 Mbits. SDRAM can be configured for 16- or
32-bit wide interface to the MCF5272 data bus. For an SDRAM array with a 32-bit data bus,
SDRAM address signals are multiplexed starting with A2. For a 16-bit data bus, address
signals are multiplexed starting with A1.
SDRAM controller bank address select outputs. Assigned to internal high-order address
signals by programming SDCR[BALOC]. This allows using SDRAM devices of different sizes
without changing the board layout. See Table 9-7.
Table 9-1. SDRAM Controller Signal Descriptions
Figure 9-1. SDRAM Controller Signals
Address Multiplexer
Dynamic Bus Sizer
SDRAM Controller
MCF5272 User’s Manual
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1
1
1
1
4
2
1
1
1
8
2
Description
D[31:0]
SDRAMCS/CS7
RAS0
CAS0
SDWE
BS[3:0]
SDBA[1:0]
SDCLKE
SDCLK
A10_PRECHG
A[22:15]
A[11:2]/SDA[9:0]
A[14:13/SDA[12:11]
MOTOROLA