mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 326

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

PLIC Registers
13.5.19 D-Channel Status Register (PDCSR)
All bits in this register are read only and are cleared on hardware or software reset. The
register is also cleared after a read operation.
The PDCSR register contains the D-channel status bits for all four ports on the MCF5272.
13-30
Bits
7–6
5
Bits
7–4
Figure 13-30. GCI C/I Channel Transmit Status Register (PGCITSR)
3
2
1
0
Name
DG1
—
Reset
Reset
Field
Field
Addr
Addr
R/W
R/W
Name
ACK3
ACK2
ACK1
ACK0
—
Figure 13-31. D-Channel Status Register (PDCSR)
Reserved, should be cleared.
D-channel grant, port 1.
0 Default reset value.
1 In IDL mode, indicates the status of DGRANT. When the external DGNT has a logic 1,
the corresponding DG1/DG0 bit is set. In GCI mode, DG1 and DG0 reflects the
inverted value of the SCIT bit. The significance of this bit is the same in IDL or GCI
mode, that is, in IDL mode when the DG bit is set, the D channel is granted. In GCI
mode when the DG bit is set, this corresponds to the GO condition. In both cases the D
channel is granted and communication may commence.
7
7
Table 13-13. PGCITSR Field Descriptions
Table 13-14. PDCSR Field Descriptions
Reserved, should be cleared.
Acknowledge, port 3.
0 Default reset value.
1 Set by the C/I channel controller to indicate that the previous C/I data has
Acknowledge, port 2. See ACK3.
Acknowledge, port 1. See ACK3.
Acknowledge, port 0. See ACK3.
—
been transmitted in two successive C/I words. The ACK bit is automatically
cleared by the CPU when the PGCITSR register has been read.
6
—
MCF5272 User’s Manual
DG1
5
MBAR + 0x37F
MBAR + 0x383
DG0
0000_0000
0000_0000
Read Only
Read Only
4
4
Description
ACK3
Description
DC3
3
3
ACK2
DC2
2
2
ACK1
DC1
1
1
ACK0
DC0
0
0
MOTOROLA