mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 500

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

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AC Electrical Specifications
23.3.2 Processor Bus Input Timing Specifications
Table 23-7 lists processor bus input timings.
Name
Timings listed in Table 23-7 are shown in Figure 23-2.
23-6
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
RSTI, TA, TEA, and INTx are synchronized internally. The setup time must be met only if recognition is needed on
a particular clock edge.
2
2
2
2
2
RSTI valid to SDCLK (setup)
TA valid to SDCLK (setup)
TEA valid to SDCLK (setup)
INTx valid to SDCLK (setup)
BKPT valid to PSTCLK (setup)
Mode selects (BUSW[1:0], WSEL, HiZ) valid to SDCLK (setup) (when RSTI asserted)
SDCLK to asynchronous control inputs (RSTI, TA, TEA, INTx) invalid (hold)
SDCLK to mode selects (BUSW[1,0], WSEL, HIZ) invalid (hold) (when RSTI asserted)
PSTCLK to asynchronous control input BKPT invalid (hold)
RSTI width low
Data input (D[31:0]) valid to SDCLK (setup)
SDCLK to data input (D[31:0]) invalid (hold)
All processor bus timings are synchronous; that is, input
setup/hold and output delay with respect to the rising edge of a
reference clock. The reference clock is the SDCLK output.
All other timing relationships can be derived from these values.
Table 23-7. Processor Bus Input Timing Specifications
MCF5272 User’s Manual
Characteristic
Control Inputs
Data Inputs
NOTE:
1
0–66 MHz
Min Max
10T
6.5
10
14
8
8
8
8
2
2
0
0
MOTOROLA
—
—
—
—
—
—
—
—
—
—
—
—
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS