mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 140

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Background Debug Mode (BDM)
5.5.2.2 Transmit Packet Format
The basic transmit packet, Figure 5-14, consists of 16 data bits and 1 control bit.
Table 5-16 describes transmit BDM packet fields.
5.5.3 BDM Command Set
Table 5-17 summarizes the BDM command set. Subsequent paragraphs contain detailed
descriptions of each command. Issuing a BDM command when the processor is accessing
debug module registers using the WDEBUG instruction causes undefined behavior.
15–0
5-18
Bits
15–0
Bits
16
16
16
C
Name
Name
Data
Data
15
S
C
Control. This bit is reserved. Command and data transfers initiated by the development system
should clear C.
Contains the data to be sent from the development system to the debug module.
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can
be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
S
0
0
1
1
1
Data. Contains the message to be sent from the debug module to the development system. The
response message is always a single word, with the data field encoded as shown above.
Data
xxxx
0xFFFF
0x0000
0x0001
0xFFFF
Table 5-16. Transmit BDM Packet Field Description
Table 5-15. Receive BDM Packet Field Description
Message
Valid data transfer
Status OK
Not ready with response; come again
Error—Terminated bus cycle; data invalid
Illegal command
Figure 5-14. Transmit BDM Packet
MCF5272 User’s Manual
D[15:0]
Description
Description
MOTOROLA
0