mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 433

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Chip Selects (CS7/SDCS, CS[6:0])
19.5 Chip Selects (CS7/SDCS, CS[6:0])
The eight chip selects, CS[7:0], allow the MCF5272 to interface directly to SRAM,
EPROM, EEPROM, and external memory-mapped peripherals. These signals can be
programmed for an address location, with masking capabilities, port size, burst capability
indication, and wait-state generation.
CS0 provides a special function as a global chip select that allows access to boot ROM at
at reset. CS0 can have its address redefined after reset. CS0 is the only chip select initialized
and enabled during reset. All other chip selects are disabled at reset and must be initialized
by device initialization software.
CS7/SDCS can be configured to access RAM or ROM or one physical bank of SDRAM.
Only CS7 can be used for SDRAM chip select.
19.6 Bus Control Signals
This section describes bus control signals.
19.6.1 Output Enable/Read (OE/RD)
The output enable/read signal (OE/RD) defines the data transfer direction for the data bus
D[31:0] for accesses to SRAM, ROM or external peripherals. A low (logic zero) level
indicates a read cycle while a high (logic one) indicates a write cycle.
This signal is normally connected to the OE pins of external SRAM, ROM, or FLASH.
19.6.2 Byte Strobes (BS[3:0])
The byte strobes (BS[3:0]) define the flow of data on the data bus. During SRAM and
peripheral accesses, these outputs indicate that data is to be latched or driven onto a byte of
the data when driven low. BSn signals are asserted only to the memory bytes used during a
read or write access.
BSn signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM,
cache, or ROM. During SDRAM accesses, these signals indicate a byte transfer between
SDRAM and the MCF5272 when driven high.
For SRAM or FLASH devices, BS[3:0] outputs should be connected to individual byte
strobe signals.
For SDRAM devices, BS[3:0] should be connected to individual SDRAM DQM signals.
Note that most SDRAMs associate DQM3 with the MSB, in which case BS3 should be
connected to the SDRAM's DQM3 input.
MOTOROLA
Chapter 19. Signal Descriptions
19-19