mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 510

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mcf5272

Manufacturer Part Number
mcf5272
Description
Mcf5272 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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1
Fast Ethernet AC Timing Specifications
23.6.2 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN,
Table 23-12 lists MII transmit channel timings.
The transmitter functions correctly up to a E_TxCLK maximum frequency of
25 MHz +1%. There is no minimum frequency requirement. In addition, the processor
clock frequency must exceed twice the E_TxCLK frequency.
The transmit outputs (E_TxD[3:0], E_TxEN, E_TxER) can be programmed to transition
from either the rising or falling edge of E_TxCLK, and the timing is the same in either case.
This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Figure 23-12 shows MII transmit signal timings listed in Table 23-12.
23-16
Num
E_TxCLK, ETxD0, and E_TxEN have the same timing in 10 Mbit 7-wire interface mode.
M5
M6
M7
M8
E_TxER, E_TxCLK)
E_TxCLK to E_TxD[3:0], E_TxEN, E_TxER invalid
E_TxCLK to E_TxD[3:0], E_TxEN, E_TxER valid
E_TxCLK pulse width high
E_TxCLK pulse width low
E_RxD[3:0] (inputs)
E_RxCLK (input)
E_RxDV
E_RxER
Figure 23-11. MII Receive Signal Timing Diagram
Table 23-12. MII Transmit Signal Timing
Characteristic
M1
MCF5272 User’s Manual
1
M2
M3
5
35%
35%
Min
M4
25
65%
65%
Max
nS
nS
E_TxCLK period
E_TxCLK period
MOTOROLA
Unit

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