mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 353

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

1
MOTOROLA
Table 14-7 gives QCR field descriptions.
14.5.8 Programming Example
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK
of 4.125 MHz. The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS
signals are used in this example.
Address
In order to keep the chip setects asserted for all transfers, the QWR[CSIV] bit must be set to control the level that
the chip selects return to after the first transfer.
Reset
Field
R/W
11–8
Bits
7–0
15
14
13
12
1. Enable all QSPI_CS pins on the MCF5272. Write PACNT with 0x0080_4000 to
2. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the
enable QSPI_CS1 and QSPI_CS3.Write PDCNT with 0x0000_0030 to enable
QSPI_CS2.
falling clock edge, and a clock frequency of 4.125 MHz (assuming a 66-MHz
CLKIN).
CONT
15
QSPI_CS
CONT
BITSE
Name
DSCK
DT
—
Figure 14-10. Command RAM Registers (QCR0–QCR15)
BITSE
Chapter 14. Queued Serial Peripheral Interface (QSPI) Module
14
Table 14-7. QCR0–QCR15 Field Descriptions
Continuous.
0 Chip selects return to inactive level defined by QWR[CSIV] when transfer is complete.
1 Chip selects remain asserted after the transfer of 16 words of data.
Bits per transfer enable.
0 Eight bits
1 Number of bits set in QMR[BITS]
Delay after transfer enable.
0 Default reset value.
1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing
Chip select to QSPI_CLK delay enable.
0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.
1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.
Peripheral chip selects. Used to select an external device for serial data transfer. More
than one chip select may be active at once, and more than one device can be connected
to each chip select. Bits 11–8 map directly to QSPI_CS[3:0], respectively. If it is desired
to use those bits as a chip select value, then an external demultiplexor must be
connected to the QSPI_CS[3:0] pins.
Reserved, should be cleared.
DT
with peripherals that have a latency requirement. The delay between transfers is
determined by QDLYR[DTL].
13
DSCK
12
11
QSPI_CS
QAR[ADDR]
Write Only
Undefined
Description
8
7
Programming Model
–
1
14-15
0