mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 127

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
PST of 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address.
Thus, the subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0
in least-to-most-significant nibble order. The PST output after the JMP instruction
completes depends on the target instruction. The PST can continue with the next instruction
before the address has completely displayed on DDATA because of the DDATA FIFO. If
the FIFO is full and the next instruction has captured values to display on DDATA, the
pipeline stalls (PST = 0x0) until space is available in the FIFO.
5.4 Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers
and the memory subsystem, the debug module contains nine registers to support the
required functionality. These registers are also accessible from the processor’s supervisor
programming model by executing the WDEBUG instruction (write only). Thus, the
breakpoint hardware in the debug module can be read or written by the external
development system using the debug serial interface or by the operating system running on
the processor core. Software is responsible for guaranteeing that accesses to these resources
are serialized and logically consistent. Hardware provides a locking mechanism in the CSR
to allow the external development system to disable any attempted writes by the processor
to the breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the
MCF5272 is using the WDEBUG instruction to access debug module registers or the
resulting behavior is undefined.
These registers, shown in Figure 5-4, are treated as 32-bit quantities, regardless of the
number of implemented bits.
PSTCLK
DDATA
PST
Figure 5-3. Example JMP Instruction Output on PST/DDATA
0x5
0x0
0x9
0x0
Chapter 5. Debug Support
default
A[3:0]
default
A[7:4]
A[11:8]
default
Programming Model
A[15:12]
default
5-5