mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 70

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Features and Enhancements
2.1.1.1 Instruction Fetch Pipeline (IFP)
The IFP generates instruction addresses and fetches. Because the fetch and execution
pipelines are decoupled by a 3 longword FIFO buffer, the IFP can prefetch instructions
before the OEP needs them, minimizing stalls.
2-2
• Two-stage IFP (plus optional instruction buffer stage)
• Two-stage OEP
— Instruction address generation (IAG) calculates the next prefetch address.
— Instruction fetch cycle (IC) initiates prefetch on the processor’s local instruction
— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of
— Decode, select/operand fetch (DSOC) decodes the instruction and selects the
— Address generation/execute (AGEX) calculates the operand address, or performs
bus.
fetch latency.
required components for the effective address calculation, or the operand fetch
cycle.
the execution of the instruction.
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
DSOC
AGEX
IAG
IC
IB
Decode & Select,
Instruction Buffer
Operand Fetch
Figure 2-1. ColdFire Pipeline
Generation,
Fetch Cycle
Generation
Instruction
Instruction
Address
Address
Execute
FIFO
MCF5272 User’s Manual
Address [31:0]
Data[31:0]
MOTOROLA