mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 303

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
13.2.3.3 D-Channel HDLC Encoded Data
When the incoming D channels contain HDLC-encoded data, they are presented on the
physical line lsb first. The Soft HDLC expects the first bit received to be aligned in the lsb
position of a byte, with the last bit received aligned in the msb position.
Because the presentation of HDLC encoded data on the physical interface is lsb first, the
lsb is right-aligned in the transmit and receive shift register.
A D-channel byte is formed by concatenating two D bits from each of four frames. This
data is also right-aligned in the D-channel receive register as shown in Figure 13-7.
13.2.3.4 D-Channel Unencoded Data
As with the B channel, a mechanism is provided to support incoming D channels containing
unencoded data, even though as of this document’s publication date, no communication
protocols using unencoded D-channel data are known.
As with unencoded (PCM encoded) B-channel data, it is assumed unencoded D-channel
information is presented on the physical line msb first. The msb is left-aligned in the
transmit and receive shift register, that is, the first bit received is aligned in the msb position
through to the last received bit of a byte that is aligned in the lsb position.
A D-channel byte is formed by concatenating two D bits from each frame over four
consecutive frames as shown in Figure 13-7. These 8 bits are also left-aligned in the
DCL
FSR
Unencoded
HDLC
Encoded
Din/Dout
Din/Dout
Figure 13-7. D-Channel HDLC Encoded and Unencoded Data.
Frame 0
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D
Chapter 13. Physical Layer Interface Controller (PLIC)
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7
Frame
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8-Bit D-Channel Receive/Transmit Register, RD, TD
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D7
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D6
D
D
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5
D5
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D
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D4
D3
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D1
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D0
Frame 3
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GCI/IDL Block
13-7