mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 118

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Instruction Cache Overview
When an external fetch is initiated and data is loaded into the line-fill buffer, the instruction
cache maintains a special most-recently-used indicator that tracks the contents of the fill
buffer versus its corresponding cache location. At the time of the miss, the hardware
indicator is set, marking the fill buffer as most recently used. If a subsequent access occurs
to the cache location defined by bits 9–4 of the fill buffer address, the data in the cache
memory array is now most-recently used, so the hardware indicator is cleared. In all cases,
the indicator defines whether the contents of the line-fill buffer or the cache memory data
array are most recently used. If the entire line is present at the time of the next cache miss,
the line-fill buffer contents are written into the cache memory array and the fill buffer data
is still most recently used compared to the cache memory array.
The fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable
references under control of CACR[CEIB]. With this bit set, a noncacheable instruction
fetch is processed as defined by Table 4-6. For this condition, the fill buffer is loaded and
subsequent references can hit in the buffer, but the data is never loaded into the cache
memory array.
Table 4-6 shows the relationship between CENB, CEIB, and the type of instruction fetch.
4.5.3 Instruction Cache Programming Model
Three supervisor registers define the operation of the instruction cache and local bus
controller: the cache control register (CACR) and two access control registers (ACR0,
ACR1). Table 4-7 shows the memory map of the CACR and ACRs. These registers have the
following characteristics:
4-12
CACR[CENB,CEIB] Type of Fetch
• The CACR and ACRs can be accessed only in supervisor mode using the MOVEC
• Addresses not assigned to the registers and undefined register bits are reserved for
Table 4-6. Instruction Cache Operation as Defined by CACR[CENB,CEIB]
instruction with an Rc value of 0x002 (CACR), 0x004 (ACR0), and 0x005 (ACR1).
future expansion. Write accesses to these reserved address spaces and reserved
register bits have no effect; read accesses return zeros.
1X
00
01
10
11
Noncacheable Cache is enabled but the linefill buffer is disabled; fetches are either word or
Noncacheable Cache and line buffer are enabled; CACR[CLNF] defines fetch size; fetches
Cacheable
N/A
N/A
Instruction cache and line-fill buffer are disabled; fetches are word or
longword in size.
Instruction cache is disabled but because the line-fill buffer is enabled,
CACR[CLNF] defines fetch size and instructions can be bursted into the
line-fill buffer.
Cache is enabled; CACR[CLNF] defines fetch size and line-fill buffer contents
can be written into the cache memory array.
longword and are not loaded into the line-fill buffer.
are loaded into the line-fill buffer but never into the cache memory array.
MCF5272 User’s Manual
Description
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