mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 200

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

SDRAM Banks, Page Hits, and Page Misses
9.4 SDRAM Banks, Page Hits, and Page Misses
SDRAMs can have up to four banks addressed by SDBA1 and SDBA0. The two uppermost
address lines of the memory space are mapped to SDBA1 and SDBA0. Specific address
lines mapped depend on the size of the SDRAM array and are defined in the SDCR.
Each of the four bank address registers holds the page address (lower bits of row address)
of an activated page. Each bank can have one open page. A device with two banks can have
two open pages. A device with four banks can have four open pages.
The lower addresses of the row address are compared against the page address register
content. If it does not match, the SDRAM controller precharges the open page on the
accessed bank and activates the new required page. After this, the SDRAM controller
executes the
is updated. This is called a page miss.
After a bank is activated, it remains activated until the next page access causing a page miss.
A precharge of a deactivated bank is allowed and simply ignored by the SDRAM.
If a memory access is to an open page only the
SDRAM. This is called a page hit.
In two-page SDRAMs, banks 2 and 3 are invalid and must not be addressed. To avoid
address aliasing, the user should restrict the chip select address range to the space available
in the SDRAMs.
9.5 SDRAM Registers
The SDRAM configuration register (SDCR) and the SDRAM timing register (SDTR) are
described in the following sections. Note that SDRAM provides a mode register that is not
part of the SDRAM controller memory model. The SDRAM mode register is automatically
configured during initialization.
9.5.1 SDRAM Configuration Register (SDCR)
SDCR is used to configure the SDRAM controller address multiplexers for the type of
SDRAM devices used on the system board.
9-6
Reset
Write
Addr
R/W
15
—
0
READ
14
MCAS
00
Figure 9-3. SDRAM Configuration Register (SDCR)
13
or
WRITE
12
—
00
command. Concurrently, the page address register of the bank
11
10
MCF5272 User’s Manual
Read/Write
BALOC
001
MBAR + 0x0182
8
READ
GSL
0
7
or
6
00
—
WRITE
5
REG
command is issued to the
4
0
INV SLEEP ACT
3
1
Read-only
2
0
MOTOROLA
0
1
R/W
INIT
0
0