mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 119

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
4.5.3.1 Cache Control Register (CACR)
The CACR controls operation of the instruction cache. It provides a set of default memory
access attributes for when a reference address does not map into spaces defined by the
ACRs. The supervisor-level CACR is accessed in the CPU address space using the MOVEC
instruction with an Rc encoding of 0x002. The CACR can be read or written when the
processor is in background debug mode (BDM).
Table 4-8 describes CACR fields.
Reset
Reset
Field CENB
Field
30–29
R/W
R/W
Bits
31
28
Rc
• The reset value column indicates the initial value of the register at reset.
• The access column indicates whether the corresponding register can be read, written
Uninitialized fields may contain random values after reset.
or both. Attempts to read a write-only register cause zeros to be returned. Attempts
to write to a read-only register are ignored.
31
15
Name
CENB
CDPI
—
Address (using MOVEC) Name Width
30
—
Table 4-7. Memory Map of Instruction Cache Registers
Enable cache.
0 Cache disabled. The cache is not operational, but data and tags are preserved.
1 Cache enabled.
Reserved, should be cleared.
Disable CPUSHL invalidation.
0 Cache disabled
1 Cache enabled
—
29
0x002
0x004
0x005
Figure 4-4. Cache Control Register (CACR)
CDPI CFRZ
28
Table 4-8. CACR Field Descriptions
27
CEIB DCM DBWE
Chapter 4. Local Memory
CACR
ACR0
ACR1
26
10
Write (R/W by debug module)
Write (R/W by debug module)
—
0000_0000_0000_0000
0000_0000_0000_0000
25
9
32
32
32
CINVA
24
8
0x002
Cache control register
Access control register 0
Access control register 1
Description
23
7
Description
—
6
DWP
5
Instruction Cache Overview
4
Reset Value
—
0x0000
0x0000
0x0000
—
2
1
CLNF
4-13
16
0