mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 368

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Register Descriptions
Table 16-4 describes USRn fields.
16.3.4 UART Clock-Select Registers (UCSRn)
The UART clock-select registers (UCSRn) select an external clock on the URT_CLK input
(divided by 1 or 16) or a prescaled CLKIN as the clocking source for the transmitter and
receiver. See Section 16.5.1, “Transmitter/Receiver Clock Source.” The transmitter and
receiver can use different clock sources. To use CLKIN for both, set UCSRn to 0xDD.
16-8
Bits
7
6
5
4
3
2
1
0
TxEMP Transmitter empty.
RxRDY Receiver ready
TxRDY
FFULL
Name
OE
RB
FE
PE
Received break. The received break circuit detects breaks that originate in the middle of a received
character. However, a break in the middle of a character must persist until the end of the next
detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. RB is valid only
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The
Parity error. Valid only if RxRDY = 1.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a
0 The transmitter buffer is not empty. Either a character is being shifted out, or the transmitter is
1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers
Transmitter ready.
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a
FIFO full. This bit is equivalent to URF[FULL].
0 The FIFO is not full but may hold unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received when the
0 The CPU has read the receiver buffer and no characters remain in the FIFO after this read.
1 One or more characters were received and are waiting in the receiver buffer FIFO.
when RxRDY = 1. Only a single FIFO position is occupied when a break is received. Further
entries to the FIFO are inhibited until RxD returns to the high state for at least one-half bit time,
which is equal to two successive edges of the UART clock.
stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1.
received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received A/D bit.
new character when the FIFO is full and a character is already in the shift register waiting for an
empty FIFO position. When this occurs, the character in the receiver shift register and its break
detect, framing error status, and parity error, if any, are lost. OE is cleared by the
STATUS
disabled. The transmitter is enabled/disabled by programming UCRn[TC].
are empty). This bit is set after transmission of the last stop bit of a character if there are no
characters in the transmitter holding register awaiting transmission.
character is sent to the transmitter shift register and when the transmitter is first enabled. If the
transmitter is disabled, characters loaded into the transmitter holding register are not sent.
FIFO is full are lost.
command in UCRn.
Table 16-4. USRn Field Descriptions
MCF5272 User’s Manual
Description
RESET ERROR
MOTOROLA