mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 312

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

PLIC Registers
13.5.2 B2 Data Receive Registers (P0B2RR–P3B2RR)
All bits in these registers are read only and are set on hardware or software reset.
The PnB2RR registers contain the last four frames of data received on channel B2.
(P0B2RR is the B2 channel data for port 0, P1B2RR is B2 for port 1, and so on.) The data
are packed from LSB to MSB.
These registers are aligned on long-word boundaries from MBAR + 0x310 for P0B2RR to
MBAR + 0x31C for P3B2RR. See Section 13.2.3, “GCI/IDL B- and D-Channel Bit
Alignment,” for the frame and bit alignment within the 32-bit word.
Figure 13-14 shows the B2 receive data registers.
13.5.3 D Data Receive Registers (P0DRR–P3DRR)
All bits in these registers are read-only and are set on hardware or software reset.
The PnDRR registers contain the last four frames of D-channel receive data packed from
the least significant bit, (lsb), to the most significant bit, (msb), for each of the four physical
ports on the MCF5272. P0DRR is the D-channel byte for port 0, P1DRR the D channel for
port 1, and so on.
13-16
Reset
Reset
Reset
Reset
Field
Field
Field
Field
Addr
Addr
R/W
R/W
R/W
R/W
31
15
31
15
Figure 13-14. B2 Receive Data Registers P0B2RR – P3B2RR
Figure 13-13. B1 Receive Data Registers P0B1RR–P3B1RR
MBAR + 0x300 (P0B1RR); 0x304 (P1B1RR); 0x308 (P2B1RR); 0x30C (P3B1RR)
MBAR + 0x310 (P0B2RR); 0x314 (P1B2RR); 0x318 (P2B2RR); 0x31C (P3B2RR)
1111_1111
1111_1111
1111_1111
1111_1111
Frame 0
Frame 2
Frame 0
Frame 2
MCF5272 User’s Manual
Read Only
Read Only
Read Only
Read Only
24
24
8
8
23
23
7
7
1111_1111
1111_1111
1111_1111
1111_1111
Frame 1
Frame 3
Frame 1
Frame 3
MOTOROLA
16
16
0
0