mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 63

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MCF5272 Architecture
The Version 2 ColdFire core has a 32-bit address bus and a 32-bit data bus. The address bus
allows direct addressing of up to 4 Gbytes. It supports misaligned data accesses and a bus
arbitration unit for multiple bus masters.
The Version 2 ColdFire supports an enhanced subset of the 68000 instruction set. The MAC
provides new instructions for DSP applications; otherwise, Version 2 ColdFire user code
runs unchanged on 68020, 68030, 68040, and 68060 processors. The removed instructions
include BCD, bit field, logical rotate, decrement and branch, integer division, and integer
multiply with a 64-bit result. Also, four indirect addressing modes have been eliminated.
The ColdFire 2 core incorporates a complete debug module that provides real-time trace,
background debug mode, and real-time debug support.
1.2.2 System Integration Module (SIM)
The MCF5272 SIM provides the external bus interface for the ColdFire 2 architecture. It
also eliminates most or all of the glue logic that typically supports the microprocessor and
its interface with the peripheral and memory system. The SIM provides programmable
circuits to perform address-decoding and chip selects, wait-state insertion, interrupt
handling, clock generation, discrete I/O, and power management features.
1.2.2.1 External Bus Interface
The external bus interface (EBI) handles the transfer of information between the internal
core and memory, peripherals, or other processing elements in the external address space.
1.2.2.2 Chip Select and Wait State Generation
Programmable chip select outputs provide signals to enable external memory and
peripheral circuits, providing all handshaking and timing signals for automatic wait-state
insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For
example, the starting address must be on a boundary that is a multiple of the block size.
Each chip select is general purpose; however, any one of the chip selects can be
programmed to provide read and write enable signals suitable for use with most popular
static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on
all chip selects, and further decoding is available for protection from user mode access or
read-only access.
1.2.2.3 System Configuration and Protection
The SIM provides configuration registers that allow general system functions to be
controlled and monitored. For example, all on-chip registers can be relocated as a block by
programming a module base address, power management modes can be selected, and the
source of the most recent RESET or BERR can be checked. The hardware watchdog
features can be enabled or disabled, and the bus time-out period can be programmed.
MOTOROLA
Chapter 1. Overview
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