mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 245

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 11-17 describes the FRSR fields.
11.5.11 Transmit FIFO Watermark (TFWR)
The TFWR register, shown in Figure 11-14, controls the amount of data required in the
transmit FIFO before transmission of a frame can begin. Setting TFWR to larger values
reduces the risk of transmit FIFO underrun due to system bus latency.
Table 11-18 describes the TFWR fields.
31–11
Reset
Reset
Bits
9–2
1–0
31–2
Field
Field
Addr
Bits
10
R/W
R/W
1–0
31
15
R_FSTART
X_WMRK
Name
Name
—
—
1
—
Figure 11-14. Transmit FIFO Watermark (TFWR)
Reserved, should be cleared.
Reserved, should be set.
Receive FIFO starting address. Address of first receive FIFO location. Acts as delimiter
between receive and transmit FIFOs.
Reserved, should be cleared.
Reserved, should be cleared.
Transmit FIFO watermark. Frame transmission begins when the number of bytes
selected by this field are written into the transmit FIFO, if an end of frame has been
written to the FIFO, or if the FIFO is full before the selected number of bytes are
written. The options are:
0X 64 bytes written to transmit FIFO
10 128 bytes written to transmit FIFO
11 192 bytes written to transmit FIFO
Table 11-18. TFWR Field Descriptions
Table 11-17. FRSR Field Descriptions
Chapter 11. Ethernet Module
0000_0000_0000_00
0000_0000_0000_0000
—
MBAR + 0x8E4
Read/Write
Read/Write
—
Description
Description
Programming Model
2
X_WMRK
1
00
16
0
11-21