mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 242

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
To generate an 802.3-compliant MII management interface write frame (write to a PHY
register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register.
Writing this pattern causes the control logic to shift out the data in the MMFR register
following a preamble generated by the control state machine. The contents of MMFR are
altered as the contents are serially shifted, and are unpredictable if read by the user. Once
the write management frame operation completes, the MII interrupt is generated. At this
time, the contents of the MMFR register match the original value written.
To generate an MII management interface read frame (read a PHY register), the user must
write {01 10 PHYAD REGAD 10 XXXX} to MMFR (the contents of the DATA field are
a don’t care). Writing this pattern causes the control logic to shift out the data in the MMFR
register following a preamble generated by the control state machine.The contents of the
MMFR register are altered as the contents are serially shifted, and are unpredictable if read
by the user. Once the read management frame operation completes, the MII interrupt is
generated. At this time the contents of the MMFR register matches the original value
written except for the DATA field, whose contents are replaced by the value read from the
PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents
are altered. Software should use the MII interrupt to avoid writing to the MMFR register
while frame generation is in progress.
11.5.8 MII Speed Control Register (MSCR)
The MSCR register, Figure 11-11, provides control of the MII clock (E_MDC pin)
frequency, allows dropping the preamble on the MII management frame and provides
observability (intended for manufacturing test) of an internal counter used in generating the
E_MDC clock signal.
Table 11-14 describes the MSCR fields.
11-18
Reset
Reset
Field
Field
Addr
R/W
R/W
31
15
Figure 11-11. MII Speed Control Register (MSCR)
0000_0000
—
MCF5272 User’s Manual
8
0000_0000_0000_0000
DIS_PREAMBLE
MBAR + 0x884
Read/Write
Read/Write
—
0
7
6
MII_SPEED
000_000
MOTOROLA
1
16
—
0
0