mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 317

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
13.5.9 Interrupt Configuration Registers (P0ICR–P3ICR)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnICR registers contain interrupt configuration bits for each of the four ports on the
MCF5272.
PLCIR0–3 IE
14–12
Bits
15
11
Reset
Addr
R/W
15
Name
GCR
Figure 13-21. Interrupt Configuration Registers (P0ICR–P3ICR)
IE
—
Bits
7-6
5-4
3-2
1-0
In loopback mode, the respective port must be enabled (using
PnCR[ON/OFF]) along with the B1 and B2 channels (using
PnCR[ENB1,
PDRQR[DCNTI] when in IDL mode, for instance). Also, if
more than one of ports 1, 2, or 3 are programmed in loopback
mode, it is necessary to program the appropriate frame sync
function using the sync delay registers discussed in
Section 13.5.21, “Sync Delay Registers (P0SDR–P3SDR).”
14
Interrupt enable. Allows the port to generate interrupts to the CPU. When cleared, the IE bit
masks all periodic and aperiodic interrupts associated with the respective port.
Reserved, should be cleared.
Interrupt enable for the C/I channel receive.
0 Interrupt masked
1 Interrupt enabled. When set, an interrupt is enabled which occurs when the corresponding
—
MBAR + 0x0358 (P0ICR); 0x035A (P1ICR); 0x035C (P2ICR); 0x035E (P3ICR)
GCR status bit is set.
Chapter 13. Physical Layer Interface Controller (PLIC)
Name
Table 13-4. P0ICR–P3ICR Field Descriptions
LM3
LM2
LM1
LM0
12
Table 13-3. PLCR Field Description
Loopback mode control, port 3.
00 Normal
01 Auto-echo
10 Local Loopback
11 Remote Loopback
Loopback mode control, port 2. See LM3.
Loopback mode control, port 1. See LM3.
Loopback mode control, port 0. See LM3.
GCR GCT GMR GMT
11
ENB2])
10
9
0000_0000_0000_0000
NOTE:
and
Read/Write
8
the
Description
Description
7
—
D
6
DTIE B2TIE B1TIE DRIE B2RIE B1RIE
5
channel
4
(using
3
2
PLIC Registers
1
13-21
0