mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 461

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 20-6 lists the bytes that should be driven on the data bus during read cycles by the
external peripheral device being accessed, and the pattern of the data transfer for write
cycles to the external data bus.
For read cycles, the entries shown as Byte X are portions of the requested operand that are
read. The operand being read is defined by the size of the transfer and A[1:0] for the bus
cycle. Bytes labeled “X” are don’t cares and are not required during that read cycle. Bytes
labeled “–” are not valid transfers.
For write cycles from the internal multiplexer of the MCF5272 to the external data bus
A[1:0] is incremented according to the transfer size. For example, if a longword transfer is
generated to a 16-bit port, the MCF5272 starts the cycle with A[1:0] set to 0x0 and reads
the first word. The address in then incremented to 0x2 and the second word is read. The data
for both word reads is taken from D[31:16]. Bytes labeled “X” are don’t cares.
Table 20-5. Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles
Table 20-4. Byte Strobe Operation for 16-Bit Data Bus—SRAM Cycles
Table 20-3. Byte Strobe Operation for 32-Bit Data Bus (Continued)
BS3 BS2 BS1 BS0
1
0
0
1
0
0
0
1
0
BS1 BS0 Access Size Data Located On
BS3 BS2
1
1
0
0
1
1
0
0
0
1
0
Chapter 20. Bus Operation
1
0
1
0
1
0
1
0
Access Type
SDRAM
SDRAM
SDRAM
Access
None
Word
None
Word
Type
Byte
Byte
Byte
Byte
Access Size Data Located On
Data Located On
Longword
Word
D[31:24]
D[23:16]
D[31:16]
D[23:16]
D[31:24]
D[31:16]
—
—
D[31:16]
D[15:0]
D[31:0]
Data Transfer Mechanism
20-7