mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 181

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
All external interrupt inputs are edge sensitive, with the active edge being programmable
through PITR. An interrupt must remain asserted for at least three consecutive rising edges
of CPU_ExtCLK to be considered valid. The priority level of each interrupt source is
programmed through the ICRs.
The MCF5272 does not support auto-vectored interrupts. Interrupt service routines for all
interrupts should have vectors in the user-defined interrupt region of the vector table
(vectors 64–255). The location of these vectors is programmable through the PIVR. For
more information on the servicing of interrupts, see Chapter 2, “ColdFire Core.” Pending
interrupts from external sources (INT[6:1]) can be cleared using the ICRs.
For an interrupt to be successfully processed, stack RAM must be available. A
programmable chip select is often used for the RAM, in which case, the RAM is not
immediately available at startup. Thus, no interrupts are recognized until PIVR is
initialized. The RAM chip select and system stack should be set up before this initialization.
If more than one interrupt source has the same interrupt priority level (IPL), the interrupt
controller daisy chains the interrupts with the priority order following the bit placement in
the PIWR, with INT1 having the highest priority and SWTO having the lowest priority, as
shown in Figure 7-8.
7.2.1 Interrupt Controller Registers
This section describes the registers associated with the interrupt controller. Table 7-2 gives
the nomenclature used for the interrupt and power management registers.
0x03C
0x030
0x034
0x038
INT1, INT2, INT3, INT4, INT5, INT6
TMR0, TMR1, TMR2, TMR3
USB0, USB1, USB2, USB3, USB4, USB5,
USB6, USB7
UART1, UART2
PLIP
PLIA
DMA
Mnemonic or Portion Thereof
Table 7-2. Interrupt and Power Management Register Mnemonics
Table 7-1. Interrupt Controller Registers (Continued)
Programmable interrupt transition register (PITR) [p. 7-7]
Programmable interrupt wakeup register (PIWR) [p. 7-8]
Chapter 7. Interrupt Controller
Interrupt source register (ISR) [p. 7-6]
Reserved
External interrupt signals 1–6.
Timers 3–0 from timer module
USB endpoint 0–7
UART1, UART2 modules
PLIC 2-KHz periodic interrupt, 2B+D data
PLIC asynchronous and maintenance channels interrupt
DMA controller interrupt
Description
Interrupt Controller Registers
Programmable interrupt
vector register (PIVR)
[p. 7-8]
7-3